It is difficult to gauge the apparent “wear and tear” or “health” of a semiconductor component as a function of time other than through statistical models generated by accelerated aging and/or stress studies. Failure analysis on packaged silicon is difficult and does not provide a way to target faults aside from memory array fails. Moreover, there are not many in-situ sensors available for root cause failure analysis.
Accelerated aging studies simulate and predict failure using numerical (statistical) methods, but do not simulate very well real world usage and do not identify a specific cause of failure or wear-down of a particular integrated circuit chip. Individual modules of an actual chip can be exposed to different environments which can contribute to unequal breakdown of the material, and this variability cannot be accurately predicted using statistical methods.
On-chip thermal sensors and ring oscillators provide data that may be used to perform regression analysis of breakdown and/or wear of chip material based on statistical models. However, these devices provide only very coarse spatial locality, or none at all.